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o1712hkpc 018-07-0002 no.a2138-1/19 specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. STK672-410C-E overview the STK672-410C-E is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? entry of external clock is enough to activate the micro step sinusoidal driver. ? the excitation mode of 2, 1-2, w1-2, 2w1-2, or 4w1-2 can be selected with the external pin. ? the 4-phase distributor switching timing can be set to occur either on both rising and falling edge detection or on rising edge detection only with an external pin (mode3). ? a phase holding function is provided to prevent phase skip during switching of excitation in the course of operation. ? the motor current is set by a voltage divider formed by an external resistor connected to the vref pin. ? the clk input pin is provided with an internal noise filte ring circuit in addition to a schmidt circuit to increase the margin for extraneous noise. ? when set low, the enable pin turns off the motor drive cu rrent for all phases and retains the phase excitation state. ordering number : ena2138 thick-film hybrid ic 2-phase stepping motor driver
STK672-410C-E no.a2138-2/19 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +5.8 v output current i oh max v dd =5v, clock 200hz 3.2 a allowable power dissipation pd max with an arbitrarily large heat sink. per mosfet 10 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta=25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 45 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih 0 to 5.8 v output current i oh tc=105 c, clock 200hz 3 a phase driver withstand voltage v dss tr1, 2, 3, 4 i d =1ma (tc=25 c) 100min v electrical characteristics at tc=25 c, v cc =24v, v dd =5.0v parameter symbol conditions min typ max unit v dd supply current i cco v dd =5.0v, enable=low vref=2v 6 10 15 ma output average current ioave r/l=3 /3.8mh in each phase 0.51 0.59 0.66 a fet diode forward voltage vdf if=1a 1.2 1.6 v output saturation voltage vsat r l =23 0.3 0.5 v v ih except for the vref pin 2.5 v input voltage v il except for the vref pin 0.6 v i ih except for the vref pin v in =5v 10 a control input pin input current i il except for the vref pin v in =0v 10 a input voltage vi pin 19 2 v dd v vref pin input current ios pin 19, v dd input 12.5 a pwm frequency fc 37.5 50 62.5 khz current distribution ratio 2w1-2 w1-2 1-2 =7/8 100 2w1-2 w1-2 =6/8 93 2w1-2 =5/8 84 2w1-2 w1-2 1-2 =4/8 71 2w1-2 =3/8 55 2w1-2 w1-2 =2/8 40 2w1-2 =1/8 19 2 vref *1 100 % notes: a fixed-voltage power supply must be used. the value of item 1 is the design target and not measured.
STK672-410C-E no.a2138-3/19 package dimensions unit:mm (typ) derating curve of motor current, i oh, vs. STK672-410C-E operating substrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalan che state, see the allowable avalanche en ergy for stk672-4** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. 29.2 25.6 (20.47) (5.0) (12.9) (5.6) 1.0 4.2 8.2 (20.4) 0.52 0.4 4.5 119 7.2 14.5 11.0 (5.0) (r1.7) (3.5) 2.0 14.5 14.4 18 1.0=18.0 3.5 0.5 0 080 20 40 60 100 70 10 30 50 90 110 2.0 3.0 2.5 1.5 1.0 i oh -tc operating substrate temperature, tc - c motor current, i oh - a 200hz 2-phase excitation hold mode
STK672-410C-E no.a2138-4/19 block diagram sample application circuit 10 stepping motor v dd =5v clk enable ro1 ro2 co2=10 co1=100 co3 d1 ro3 simplified power-on reset circuit (this circuit cannot be used to detect drops in the power-supply voltage) 11 17 12 15 13 14 19 1 3 5 4 2 6 16 18 9 excitation mode control rising edge / falling edge detection voltage division ratio phase advance counter reference clock generator pwm control rc oscillator poewr on reset current distribution ratio switching 9 mode1 mode2 10 11 clk 12 cwb 17 enable s.g 18 v ss 16 sub v dd 15 pseudo sin wave generator 13 mode3 14 reset phase excitation drive signal generator 7 8 19 vref nc nc + - + - a ab b bb 4531 p.g2 p.g1 2 6
STK672-410C-E no.a2138-5/19 precautions [internal mosfet destruction] ? the internal mosffet gate voltage is supplied from the 5v power supply. if the 5v power supply voltage is below its allowable operating voltage range, the resultant in sufficient gate drive state may destroy the mosfet. [gnd wiring] ? to reduce noise in the 24v system, locate the ground side of co1 in the circuit above as close as possible to pins 2 and 6 on the hybrid ic. also, to assure that the current is set accurately, the vr ef ground side must be connected to a ground point that is a shared connection between the groun d pin (pin 18, s.g) used for the current setting and p.g1 and p.g2. ? if the v ss pin (pin 16) near the driver, the s.g pin (pin 18), the p.g1 pin (pin 2), and the p.g2 pin (pin 6) cannot be connected to a single-poin t ground, connect the v ss pin to the control system s.gnd, and the s.g pin to the p.g1 pin and the p.g2 pin. [input pins] ? the voltage range for the input pins is -0.3 to +5.8v. design applications so that voltages lower than -0.3v and higher than 5.8v are never applied to the input pin. ? do not connect any of the nc pins (pins 7, and 8) shown in the internal equivalent circuit block diagram to the circuit pattern on the printed circuit board. ? connect a resistor (1k ) so that discharge energy of capac itor co2 does not enter the hybrid ic. ? inputs to pins 10, 11, 12, 13, 14, 15, and 17 are signal whose high level is 2.5v. both ttl and cmos inputs are supported. ? internal pull-up resistors are not provided for the input pins. if this hybrid ic's inputs are controlled by open-collector type circuits, external pull-up resistors must be provided. ? if resistors are connected in series with the inputs, insert capacitors between the inputs and ground to prevent malfunctions due to the hybrid ic's switching noise. ? in the application circuit example, a simple rese t circuit is formed by d1, ro3, co2, and a 1k resistor. this circuit will not create a reset signal if the 5v supply voltage drops briefly. this circuit structure requires the 5v supply voltage to fall below 0.6v to operate. connect the hybrid ic directly to v dd to use the hybrid ic's power on reset function. ? a power on reset operation must be applied when the 5v power supply level is first applied. [vref current setting] ? to reduce the influence of input impedance 200k input current of the terminal vref, ro1 recommends about 1k . ? we recommend using the following circuit to temporarily reduce the motor current. ? although the driver provides a constant current control function, it does not have an overcurrent protection function to assure that the maximum output current, i oh max, is not exceeded. if vref is set by mistake to a voltage that such that i oh max is exceeded, the driver will draw excessi ve current and the device will be destroyed. ? if the vref pin (pin 19) is left open, the vref voltage will be set to about 2.5v. with the stk672-400, the motor current will then be about 1.8a. with the stk672-410, the motor current will be about 3.2a. these current settings are close to i oh max. 5v vref 5v ro2 ro1 ro1 ro2 r3 r3 vref
STK672-410C-E no.a2138-6/19 [setting the motor current] the motor current is set by the hybrid ic's pin 19v, vref. the formula shows below gives the relationship between i oh and vref. vref = v dd -(i oh rs k) (1) k: 6.55 (voltage divider ratio) rs: 0.122 (hybrid ic internal current dete ction resistance: precision = 3%) model of the motor phase current flowing into the hybrid ic function table m2 0 0 1 1 m1 m3 0 1 0 1 phase switching clock edge timing 1 2 phase excitation 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation clk rising edge 0 1-2 phase excitation w1-2 phase excitation 2w1-2 phase excitation 4w1-2 phase excitation both clk edges cwb pin enable and reset pins forward reverse enable motor current cut: low cwb 0 1 reset active low 0a i oh i ol ioave
STK672-410C-E no.a2138-7/19 timing charts m1 m2 m3 reset cwb clk a b a 0 0 100% 72% 100% 72% vref b vref a 0 1 b 2 phase excitation timing chart (m3=1) 1-2 phase excitation timing chart (m3=1) w1-2 phase excitation timing chart (m3=1) 2w1-2 phase excitation timing chart (m3=1) m1 m2 m3 reset cwb clk a b a 0 0 0 1 1 b m1 m2 m3 reset cwb clk a b a 0 1 0 100% 72% 100% 72% vref a vref b 0 1 b m1 m2 m3 reset cwb clk a b a 0 0 0 1 1 1 b mosfet gate signal mosfet gate signal mosfet gate signal mosfet gate signal comparator reference voltage 100% 72% 41% 100% 93% 93% 72% 41% vref a vref b comparator reference voltage comparator reference voltage 100% 93% 84% 72% 55% 41% 21% 100% 93% 84% 72% 55% 41% 21% comparator reference voltage vref a vref b
STK672-410C-E no.a2138-8/19 m1 m2 m3 reset cwb clk a b a 0 0 100% 72% 100% 72% vref b vref a 0 b 1-2 phase excitation timing chart (m3=0) w1-2 phase excitation timing chart (m3=0) 2w1-2 phase excitation timing chart (m3=0) 4w1-2 phase excitation timing chart (m3=0) mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 0 100% 72% 55% 41% 21% 93% 84% 100% 72% 55% 41% 21% 93% 84% vref a vref b 0 1 b mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 1 0 100% 72% 93% 41% 93% 100% 72% 41% vref a vref b 0 b mosfet gate signal m1 m2 m3 reset cwb clk a b a 0 0 100% 93% 84% 72% 55% 41% 21% 97% 88% 78% 64% 48% 31% 12% 100% 93% 84% 72% 55% 41% 21% 97% 88% 78% 64% 48% 31% 12% 0 1 1 b mosfet gate signal vref a vref b comparator reference voltage comparator reference voltage comparator reference voltage comparator reference voltage
STK672-410C-E no.a2138-9/19 usage notes 1. input pins and functional overview [input pins] hybrid ic pin no. symbol function pin type 19 vref current setting input impedance: 200k (typical) 10, 11, 17 mode1, mode2, mode3 excitation mode setting ttl level schmitt input 12 clk phase switching clock (speed command) same as the above 13 cwb motor direction setting same as the above 14 reset system reset same as the above 15 enable motor current off same as the above 2. input signal functions [clk (phase switching clock)] (1) input frequency: dc to 50khz (2) minimum pulse width: 10 s (3) pulse width duty: 40 to 60% (4) pin circuit type: ttl level schmitt trigger input (5) a multi-stage noise exclusion circuit is included. (6) function ? m3:1 when m3 is 1:the excitation phase is advanced one step on each clk signal rising edge. ? m3:0 when m3 is 0:the excitation phase is advanced one step alternately on each clk si gnal rising or falling edge. ? timing chart [cwb (motor direction setting)] (1) pin circuit type: ttl level schmitt trigger input (2) function ? when cwb = 0: the motor turns in the clockwise direction ? when cwb = 1: the motor turns in the counterclockwise direction (3) note: the value of the cwb input must not be changed in the period from 7 s before a clk input rising or falling edge until 7 s after that edge. [enable (forces the excitation drive outputs a, ab, b, and bb to the off state and selects the hybrid ic's internal state to be operating or hold)] (1) pin circuit type: ttl level schmitt trigger input (2) function a) when enable is 1: normal operating state b) when enable is 0: the motor current is turned off and the excitation drive output is turned off forcibly. at this time, the hybrid ic's system clock is stopped and the hybrid ic is not influenced by changes to any input pins other than the reset input. excitation counter up/down clk input system clock phase excitation counter clock control output timing control output switching timing
STK672-410C-E no.a2138-10/19 [mode1, mode2, and mode3 (excitation mode and timing mode selection)] (1) pin circuit type: ttl level schmitt trigger input (2) excitation mode selection (see the application circuit example page for details on excitation mode selection.) (3) valid mode setting timing: do not change the mode within the 7 s period around any rising or falling edge on the clk input signal. mode setting acquisition timing [reset (whole system reset)] (1) pin circuit type: ttl level schmitt trigger input (2) function: the reset signal to this hybrid ic's internal se quencer can be selected to be either the hybrid ic internal power-on reset function or an external signal. to operate the hybrid ic inte rnal sequencer from the hybrid ic internal power-on reset signal, connect the hybrid ic's pin 14 to v dd . the hybrid ic internal reset signal is generated with a timing such that it is output to internal circuits when v dd is in the range 2.9 to 3.9v. alternatively, if an external signal is used as the reset signal, it must have the timing relative to the rise of the v dd voltage shown in the figure below. note that th e reset pulse must have a pulse width of at least 1ms. ? external reset and power supply application sequence clk input system clock mode settin g mode switching clock ic internal settin g state phase excitation clock mode switching timing phase excitation counter up/down 4.5v v dd : 5v power supply (hybrid ic pin 9) reset: hybrid ic pin 14 at least 1ms
STK672-410C-E no.a2138-11/19 [vref (sets the current that is used as th e reference for setting the output current)] (1) pin circuit type: analog input (diffe rential amplifier). input resistance: 200k (2) function: the input voltage must be in the voltage range from the control system power supply v dd to 2v. note that there is a resi stance component (200k , typical) in this hybrid ic's input and that therefore an input current occurs. if the vref voltage structure is formed as a resistor voltage divider, that circuit must be designed to take that input current into account. the input current is 12.5 a (typical). note that this is the current when vref is 5v. the input current falls according to the formula shown below when the vref voltage is below that level. ios=vref/(200k+200k) --------- (1) ? input circuit structure 200k 2.5v to dac hybrid ic pin 19 200k : 1% vref STK672-410C-E 200k ios=12.5 a
STK672-410C-E no.a2138-12/19 3. calculating STK672-410C-E hic internal power loss hic internal loss calculation of STK672-410C-E the internal average power loss in the excitati on modes of stk672-400 is calculated as follows: [excitation modes] 2 phase excitation mode 2pdav = (vsat+vdf) 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) --------------------------- (3-1) 1-2 phase excitation mode 1-2pdav = (vsat+vdf) 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) ---------------------- (3-2) w1-2 phase excitation mode w1-2pdav =0.64[(vsat+vdf) 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3)] ------------- (3-3) 2w1-2 phase excitation mode 2w1-2pdav =0.64[(vsat+vdf) 0.0625 clock i oh t2+0.0625 clock i oh (vsat t1+vdf t3)] ------ (3-4) 4w1-2 phase excitation mode 4w1-2pdav =0.64[(vsat+vdf) 0.0625 clock i oh t2+0.0625 clock i oh (vsat t1+vdf t3)] ------ (3-5) at motor hold hold pdav = (vsat+vdf) i oh ---------------------------------------------------------------------------------------------- (3-6) note: 2-phase 100% conductance is assumed in equation (3-6). vsat: synthetic voltage of ron voltage drop + synthetic voltage of current detection resistance vdf: synthetic voltage of fet body diode vdf + synthetic voltage of current detection resistance clock: input clock clk (reference frequency before splitting into four phases) t1, t2, and t3 are waveforms shown in the following figure: t1: time till the winding current reaches the set value (i oh ). t2: time for the constant-current control (pwm) region t3: time from the phase signal off up to regenera tive consumption of the counter electromotive force motor com current waveform model t1= (-l/(r+0.3)) ln (1-((r+0.3)/v cc 1) i oh )) ---------------------------------------------------------------- (3-7) t3= (-l/r) ln ((v cc 1+0.3)/(i oh r+v cc 1+0.3)) ---------------------------------------------------------------- (3-8) v cc 1: motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) i oh 0a t1 t2 t3
STK672-410C-E no.a2138-13/19 phase signal on time t and constant-current control time t2 in excitation modes (1) 2 phase excitation mode t2 = (2 clock) - (t1 + t3)(3-9) (2) 1-2 phase excitation mode t2 = (3 clock) - t1(3-10) (3) w1-2 mode t2 = (7 clock) - t1(3-11) (4) 2w1-2 phase excitation (4w1-2 phase excitation) t2 = (15 clock) - t1(3-12) enter the value of vsat and vdf from vsat vs i oh and vdf vs i oh graphs for the set current value of i oh . compare the hic average power lo ss thus determined with the tc vs pd graph to determine whether the heat sink is necessary. see the section on stk672-400c-e thermal design s ection later in this document for details on heat sink design. the value hic for the average powe r loss pdav is the loss when the device is not in the avalanche state. to add the avalanche state loss, add the stk6 72-400d-e avalanche energy allowable value from equation (2) to the pdav value above. when the fin is not used, the hic substrate temper ature tc changes because of th e effect of air convection, etc. be sure to check temperature rise with the set. [calculating pavl, the average powe r loss in the avalanche state] the average power loss in the avalanche state, pavl, is give n by formula (4-2), which is the expression for the loss, pavl, in the avalanche state during constant-current chopping operation multiplied by the chopping frequency. pavl=v dss iavl 0.5 tavl fc(4-2) fc: hz (use the maximum pwm frequency for the stk672-400 series.) the values for v dss , iavl, and tavl must be observed with an osc illoscope in an actual operating circuit based on the stk672-400 series device, and those values must then be substituted into these equations. the pavl added differs for th e different excitation modes: for modes other than 2 phase excitation, multiply pavl by the following constant and then add to the hybrid ic internal average power loss. for 1-2 phase excitation and higher modes: pavl(1)=0.7 pavl (3-13) for 2 phase excitation mode and motor hold mode: pavl(1)=1 pavl (3-14)
STK672-410C-E no.a2138-14/19 STK672-410C-E output saturation voltage, vsat - output current, i oh STK672-410C-E forward voltage, vdf -output current, i oh substrate temperature rise, tc (no heat sink) - internal average power dissipation, pdav 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02551 0 1.0 1.5 2.0 0.5 2.5 3.0 3.5 4.0 0.8 0.6 0.4 0.2 0 1.2 1.0 vsat - i oh output current, i oh - a output saturation voltage, vsat - v t c = 1 0 5 c 2 5 c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.4 0.2 0 1.6 1.0 1.2 1.4 0.8 0.6 vdf- i oh output current, i oh - a forward voltage, vdf - v tc = 2 5 c 1 0 5 c
STK672-410C-E no.a2138-15/19 4. STK672-410C-E allowabl e avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an STK672-410C-E hybrid ic, the waveforms shown in figure 1 below result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-400 series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-400 seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (4-1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (4-1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (4-1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-400 series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (4-2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (4-1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (4-2) fc: hz units (fc is set to th e pwm frequency of 62.5khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-400 series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=0.8a, tavl=0.2 s when using a STK672-410C-E driver, the result is: pavl=110 0.8 0.5 0.2 10 -6 62.5 10 3 =0.55w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (4-2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
STK672-410C-E no.a2138-16/19 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the STK672-410C-E when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during STK672-410C-E avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 3w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. consider using these devices in the usage ranges fo r an operating substrate temperature tc of 105c. i oh : motor current peak value v ds i d itf02558 01.0 0.5 1.5 2.0 2.5 3.0 1.0 0.5 0 3.0 1.5 2.0 2.5 p a vl - i oh motor phase current, i oh - a average power loss in the avalanche state, p a vl - w
STK672-410C-E no.a2138-17/19 5. STK672-410C-E thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current in creases. to calculate pdav, refer to ?calculating internal hic loss for the STK672-410C-E? in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations. figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (4-2), ?allo wable stk672-400 avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side)
STK672-410C-E no.a2138-18/19 figure 2 substrat e temperature rise, tc - internal average power dissipation, pdav figure 3 heat sink area (thickness: 2mm) - c-a 2 1.0 2 100 7 10 35 2 7 35 1000 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w itf02554 5 100 3 10 7 2 5 3 7 w i t h n o s u r f a c e f i n i s h w i t h a f l a t b l a c k s u r f a c e f i n i s h 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c 50 70 60 40 30 itf02553
STK672-410C-E no.a2138-19/19 6. STK672-410C-E ambient te mperature ta package power loss pdpk derating curve the package power loss pdpk is the internal average power loss pdav that is allowed without a heat sink. the figure below shows the power loss pdpk that is allo wable as the ambient temperature ta changes. at ta=25c a power loss of 3.1w is allowa ble, and at ta=60c, 1.75w is allowable. STK672-410C-E package power loss pdpk (no heat sink) - ambient temperature ta ps sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. this catalog provides information as of october, 2012. specifications and information herein are subject to change without notice. 1.0 0.5 0 080 20 40 60 100 120 pdpk - ta ambient temperature,ta - c allowable power dissipation, pdpk - w 2.5 3.0 3.5 2.0 1.5 itf02511

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